1. Field of the Invention
The present invention relates to a track and hold circuit, and more particularly to a highly accurate, low-distortion track and hold circuit for use in a front end of an analog-to-digital converter.
2. Description of the Related Art
A track and hold circuit is one of basic analog circuits for use at the front end of an analog-to-digital converter, and serves to sample the value of a signal that changes continuously with time, at discrete time intervals. The track and hold circuit causes signal distortion for three reasons, which will be described below using a most fundamental conventional track and hold circuit shown in FIG. 3 of the accompanying drawings.
(A) Variation of Time Required for Charging a Holding Capacitor in a Track Mode:
The illustrated track and hold circuit shown in FIG. 3 comprises two amplifiers 101, 102, a MOS transistor 103 operable as an FET switch, a holding capacitor 104, and a clock source 105. The MOS transistor 103 has a bulk terminal connected to a common potential point (ground). When the MOS transistor 103 is turned on, a base resistance Ron depends on a block voltage, i.e., a gate drive voltage V"PHgr" of the MOS transistor 103, an input voltage Vin applied to the drain thereof, and a threshold voltage Vth, and is related to these parameters as follows:
Ron=1/{xcex2(V"PHgr"xe2x88x92Vinxe2x88x92Vth)}xe2x80x83xe2x80x83(1)
Where xcex2 represents a constant determined by the fabrication process and is expressed by xcex2=xcexcCoxW/L (xcexc: mobility, Cox: gate oxide film capacitance, W: gate width, L: gate length).
Therefore, when the input voltage Vin varies, the base resistance Ron also varies, and hence the time constant for time required for charging the holding capacitor 104, which is given by Ronxc3x97CH (CH is the capacitance of the holding capacitor 104). The signal dependency of the base resistance Ron of the MOS transistor 103 which depends on the input voltage Vin that is supposed to vary, causes time for charging the holding capacitor 104 to vary, resulting in harmonic distortion.
(B) Variation of Timing Upon Mode Transition:
When the input voltage Vin varies, the timing of transition from the track mode to a hold mode varies as shown in FIG. 4 of the accompanying drawings. Specifically, the voltages need to satisfy the condition V"PHgr"xe2x89xa7Vin+Vth upon transition from the track mode to the hold mode, and need to satisfy the condition V"PHgr"xe2x89xa6Vin+Vth upon transition from the hold mode to the track mode. Therefore, if the input voltage Vin is large, the timing of transition from the track mode to the hold mode is delayed, and the timing of transition from the hold mode to the track mode is advanced. Conversely, if the input voltage Vin is small, the timing of transition from the track mode to the hold mode is advanced, and the timing of transition from the hold mode to the track mode is delayed. The signal-dependent timing variation also tends to result in harmonic distortions.
(C) Charge Injection Upon Mode Transition:
As shown in FIG. 5 of the accompanying drawings, when the track mode changes to the hold mode, charges stored under the gate of the MOS transistor 103 are discharged. Specifically, charge Q1 injected into the gate when the MOS transistor 103 is turned on is discharged when the MOS transistor 103 is turned off. Furthermore, charge Q2 stored in a parasitic capacitance Cgs between the gate and source of the MOS transistor 103 when the MOS transistor 103 is turned on is discharged when the MOS transistor 103 is turned off. When the MOS transistor 103 is turned off, these charges Q1, Q2 flow into the holding capacitor, possibly causing harmonic distortion. It is known that the charges Q1, Q2 are determined according to the following equations:
Q1=xe2x88x92CoxA(V"PHgr"xe2x88x92Vinxe2x88x92Vth)xe2x80x83xe2x80x83(2)
where Cox represents the gate oxide film capacitance per unit area of the MOS transistor 103, A represents the gate area of the MOS transistor 103, V"PHgr" represents the clock voltage, Vin represents the input voltage Vin applied to the drain of the MOS transistor 103, and Vth represents the threshold voltage.
Q2=xe2x88x92Cgs(Vin+Vth)xe2x80x83xe2x80x83(3)
where Cgs represents the gate-to-source capacitance of the MOS transistor 103, and Vth represents the threshold voltage. The gate-to-source capacitance Cgs depends on the input voltage Vin as expressed by the following equation:
Cgs=Cgs0/{1xe2x88x92(V"PHgr"xe2x88x92Vinxe2x88x92Vth)"psgr"0}xc2xdxe2x80x83xe2x80x83(4)
where "psgr"0 represents a built-in potential, and Cgs0 represents the value of the gate-to-source capacitance when Vgs=0.
As described above, both the charges Q1, Q2 depend on the input voltage Vin, and are responsible for harmonic distortion. Particularly, the charge Q2 depends nonlinearly on the input voltage Vin.
Attempts have been made to reduce distortion caused by variations in the input voltage. According to one effort, the gate drive voltage is increased to reduce the dependency of the on resistance upon the input signal, and the MOS transistor is arranged as a CMOS switch to reduce the on resistance. These proposals require a necessary drive voltage to be increased, as is apparent from the characteristics of the MOS transistor, and an increased drive voltage goes against the recent tendency toward lower voltages for circuit design, and results in a large feedthrough of charges. In addition, a high-speed PMOS is needed, and the problem of timing deviations due to variations in the threshold voltage Vth remains unsolved. Accordingly, the above proposals have proven unsatisfactory.
An effort has also been made to change the gate voltage depending on the level of the input signal. Examples of such an effort are described in Application Note, dated Mar. 10, 1997, relating to AN301, of Siliconix division of TEMIC Semiconductors, and Japanese Patent No. 2833070 (Japanese Patent Laid-open No. Heisei 3-219724). However, these circuit arrangements require a voltage source ranging from 10 to 15 volts, and do not lend themselves to a system LSI device which needs a lower operational voltage, though they can be used for measuring instruments. In addition, the circuit arrangements have a complex driver circuit.
It has also been proposed to use a dummy switch to reduce the charge injection. For example, reference should be made to Japanese Patent Laid-open No. Heisei 10-312698. According to the proposed scheme, another MOS transistor is inserted between the MOS transistor 103 and the amplifier 101 at the output stage or ground, for absorbing at least part of the charge flowing into the holding capacitor. One problem with the proposal is that the timing to drive the added MOS transistor needs to be controlled finely, and a more essential problem is that it is difficult to handle the charge injection quantitatively.
It is therefore an object of the present invention to provide a track and hold circuit which can operate at a lower voltage and can reduce distortions in waveforms that are held by the circuit.
According to the present invention, the signal distortion of a track and hold circuit is lowered by controlling a bulk potential or substrate potential of a MOS transistor switch.
According to the present invention, there is provided a track and hold circuit which includes a MOS transistor switch and a holding capacitor, the arrangement being such that a bulk potential of the MOS transistor switch is changed in phase with an input signal.
According to the present invention, there is also provided a track and hold circuit which includes a MOS transistor switch for selectively transmitting and blocking an input voltage depending on a gate voltage thereof, a holding capacitor electrically connected to the MOS transistor switch, for generating an output voltage, and a level shifting circuit for supplying a potential depending on an input signal to a bulk terminal of the MOS transistor switch. The track and hold circuit further may include an amplifier having an input terminal and an output terminal, and a terminal of the holding capacitor which is connected to the MOS transistor switch may be connected to the input terminal of the amplifier, and the output terminal of the amplifier may be used as an output terminal of the track and hold circuit. The potential supplied to the bulk terminal of the MOS transistor switch is preferably in phase with the input signal. A buffer amplifier may be connected between the MOS transistor switch and an input terminal.
According to the present invention, there is further provided a track and hold circuit comprising an amplifier having an inverting input terminal for being supplied with an input signal from an input signal terminal in a track mode, a holding capacitor having a terminal electrically connected to an output terminal of the amplifier, and another terminal electrically connected to the inverting input terminal of the amplifier in a hold mode, a first MOS transistor switch connected between the other terminal of the holding capacitor and the inverting input terminal, a second MOS transistor switch connected between the other terminal of the holding capacitor and a common potential point, a third MOS transistor switch connected between the input signal terminal and the inverting input terminal, a fourth MOS transistor switch connected between the input signal terminal and the common potential point, a first level shifting circuit having an output terminal connected to bulk terminals of the first and second MOS transistors, and a second level shifting circuit having an output terminal connected to bulk terminals of the third and fourth MOS transistors.
The first level shifting circuit may have an input terminal connected to the output terminal of the amplifier via a capacitor having substantially the same capacitance as the holding capacitor. Alternatively, the first level shifting circuit may have an input terminal connected to a node shared by the first MOS transistor switch and the second MOS transistor switch.
The first level shifting circuit may supply a potential variation with a phase opposite to that of the input signal to the bulk terminals of the first and second MOS transistor switches, and the second level shifting circuit may supply a potential variation in phase with the input signal to the bulk terminals of the third and fourth MOS transistor switches.